1. Field of the Invention
The present invention relates to the fabrication of a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including the formation of a spacer on the sidewalls of a gate.
2. Description of the Related Art
A spacer formed around a gate of a complementary metal oxide semiconductor field effect transistor (CMOS FET) is typically used as an implant mask in a self aligned drain and source implantation. In addition, the spacer is used to isolate drain/source electrodes from a gate electrode when the drain/source electrodes are formed through a silicide formation process.
In order to enhance the reliability of functions of the gate spacer and prevent the occurrence of defects in a lower substrate when the spacer is formed, a multi-layered spacer may been introduced and some layers of the spacer may be removed so as to form the spacer in an xe2x80x9cLxe2x80x9d shape on the sidewalls of the gate. Such a method for fabricating the spacer has been suggested in U.S. Pat. No. 5,783,475 of Shrinath Ramaswami (issued on Jul. 21, 1998).
This method for fabricating the spacer is employed for enhancing the reliability of the distribution of doped impurities in a LDD (lightly doped drain) when drain/source regions are formed of the LDD by self aligned drain and source implantation. Such a method of fabrication has been suggested in U.S. Pat. No. 5,766,991 of The-Yi James Chen (issued on Jun. 16, 1998).
Actually, however, if a spacer having an xe2x80x9cLxe2x80x9d shape is used in the fabrication of a transistor device such as a field effect transistor (FET), the removal of some layers of the multilayered spacer is inevitably accompanied by the recessing of an isolating layer.
FIGS. 1 and 2 are sectional views for explaining a conventional method for fabricating a spacer.
Referring to FIG. 1, an isolating layer 45 is formed on a semiconductor substrate 10. The isolating layer 45 may be formed through a well-known process such as shallow trench isolation (STI). A buffer layer 41 may be formed as an interface between the isolating layer 45 and the semiconductor substrate 10. A gate dielectric layer 21 is formed on an active region 11 of the semiconductor substrate 10 defined by the isolating layer 45, and a gate 25 is formed on the gate dielectric layer 21.
An xe2x80x9cLxe2x80x9d shaped first spacer 50 is formed of silicon nitride on both sides of the gate 25, and a second spacer layer 60 is formed of silicon oxide as a disposable spacer on the first spacer 50. An insulating layer 30 composed of silicon oxide may be formed between the gate 25 and the first spacer 50.
Referring to FIG. 2, the second spacer layer 60 is removed after being used as an implant mask during the drain and source region (not shown) implantation process. The isolating layer 45 may also be etched with removal of the second spacer layer 60. According to the conventional method, the second spacer layer 60 is removed through wet etching in which an etchant is provided to the surface of the isolating layer 45 of the shallow trench isolation (STI). Since both the second spacer layer 60 and the isolating layer 45 of the STI are formed of silicon oxide, the isolating layer 45 is unintentionally etched through the wet etching and thus the recess of the isolating layer 45 occurs due to the etching of the isolating layer 45.
If recessing of the isolating layer 45 occurs, the silicide layer (not shown) for the drain/source electrodes may penetrate into a channel region beneath the gate 25. The penetration occurs along the boundary between the channel region and the isolation layers 45, beneath the extended gate 25. The penetration of the silicide layer into the channel region beneath the gate 25 may cause leakage current during the operation of the transistor, wherein a main path of the leakage current is formed along a boundary between the channel region and the isolating layer 45.
Therefore, when a thinner xe2x80x9cLxe2x80x9d shaped spacer (e.g., the first spacer 50 of FIG. 1) is formed with introducing the disposable spacer (e.g., the second spacer layer 60 of FIG. 1), the prevention of the recess of the isolating layer 45 of the STI becomes the most important task.
It is an object of the present invention to provide a method for fabricating a spacer that is capable of preventing the recessing of an isolating layer due to wet etch for removing a disposable spacer when a thinner spacer is required to be formed on the sidewalls of a gate by using the disposable spacer.
According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device including a gate spacer. The method includes forming an insolating layer which defines an active region on a semiconductor substrate, forming a gate on the active region of the semiconductor substrate, forming of a first insulating material a first spacer layer which covers the gate and is extended to cover the isolating layer, forming of a second insulating material a second spacer layer on the first spacer layer, forming a second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer, forming a first spacer from a portion of the first spacer layer which is protected by the second spacer and a protection layer which protects the insolating layer by allowing a portion of the first spacer having a reduced thickness to remain by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, selectively removing the second spacer and forming a gate spacer which is formed of the first spacer by removing the remaining portion of the protection layer.
In one embodiment, forming the first spacer layer further comprises depositing silicon nitride as the first insulating material. Forming the second spacer layer further comprises depositing silicon oxide as the second insulating material so that the silicon oxide can be selectively etched with respect to the silicon nitride.
In one embodiment, the partial etch for forming the protection layer is a wet etch using phosphoric acid which selectively etches the silicon nitride with respect to the silicon oxide. In one embodiment, the partial etch for forming the protection layer is a dry etch using plasma which is excited by a reactive gas including a fluoric carbon gas, a fluoric hydro carbon gas and an oxygen gas which selectively etch the silicon nitride with respect to the silicon oxide.
Selectively removing the second spacer can be performed by a wet etch using fluoric acid which selectively etches the silicon oxide with respect to the silicon nitride.
Removing the protection layer can be performed by a wet etch using phosphoric acid which etches the silicon nitride forming the protection layer.
In one embodiment, the method further comprises forming an insulating layer composed of silicon oxide beneath the first spacer layer. Forming the insulating layer further comprises growing an oxide layer of thermal oxide on the semiconductor substrate.
Selectively removing the second spacer can include anisotropically etching the second spacer layer so as to expose a portion of the first spacer layer.
In accordance with another aspect, the method for fabricating a semiconductor device of the invention includes forming an insolating layer which defines an active region on a semiconductor substrate, forming a gate on the active region of the semiconductor substrate, forming a first spacer layer which covers the gate and is extended to cover the isolating layer, of a first insulating material, forming a second spacer layer on the first spacer layer of a second insulating material, forming a second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer, forming a first spacer by a portion of the first spacer layer which is protected by the second spacer and a protection layer which protects the insolating layer by allowing a portion having a reduced thickness to remain by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, implanting an impurity layer forming drain/source regions with a mask of the second spacer, selectively removing the second spacer, forming a gate spacer which is formed of the first spacer by removing the remaining portion of the protection layer and forming a self aligned silicide layer on the semiconductor substrate exposed by the gate spacer.
Here, the method is characterized in that the impurity layer which is implanted using the second spacer as a mask is an impurity layer having a high density and further comprises implanting an impurity layer having a low density in which the drain and source regions have a lightly doped drain using the gate as a mask. The method is characterized in that the impurity layer which is implanted using the second spacer as a mask is an impurity layer having a high density and further comprises implanting a impurity layer having a low density in which the drain and source regions have a lightly doped drain using the gate spacer as a mask.
According to the present invention, it is possible to prevent the recessing of the isolating layer due to the wet etching for removing the disposable spacer when the thinner spacer is formed on the sidewalls of the gate by using the disposable spacer.